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MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
6
MK2069-01
REV K 051310
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
Where:
FT Divider = 1 to 64
RT Divider = 1 to 4
The frequency range of TCLK is set by the operational range
of the internal VCO circuit and the output divider selections:
Where:
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
A higher VCO frequency will generally produce lower phase
noise and therefore is preferred.
MK2069-01 Loop Response and JItter
Attenuation Characteristics
The MK2069-01 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock. This
operation is known as jitter attenuation. The low-pass
frequency response of the VCXO PLL loop is the
mechanism that provides input jitter attenuation. Clock jitter,
more accurately called phase jitter, is the overall instability
of the clock period which can be measured in the time
domain using an oscilloscope, for instance. Jitter is
comprised of phase noise which can be represented in the
frequency domain. The phase noise of the input reference
clock is attenuated according to the VCXO PLL low-pass
frequency response curve. The response curve, and thus
the jitter attenuation characteristics, can be established
through the selection of external MK2069-01 passive
components and other device setting as explained in the
following section.
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characterizes set by the
user. This includes the values of RS, CS, CP and RSET as
shown in the External VCXO PLL Components figure on this
page.
The VCXO PLL loop bandwidth is approximated by:
Where:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps
(see table on page 7)
KO = VCXO Gain in Hz/V
(see table on page 8)
SV Divider = 1,2,4,6,8,10,12 or 16
FV Divider = 1 to 4096
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by CP. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO
PLL by the phase detector frequency, the following general
rule should be observed:
.
The PLL loop damping factor is determined by:
Where:
CS = Value of capacitor CS in loop filter in Farads
f(TCLK)
FT Divider
RT Divider
----------------------------
f(VCLK)
×
=
f(TCLK)
f(VC0)
ST Divider
-----------------------
=
NBW(VCXO PLL)
R
S
I
CP
×
K
O
×
2
π SV Divider
×
FV Divider
×
-----------------------------------------------------------------------------
=
NBW(VCO PLL)
f(Phase Detector)
20
---------------------------------------
≤
DF(VCLK)
R
S
2
------
I
CP
C
S
×
K
O
×
SV Divider
FV Divider
×
---------------------------------------------------------------
×
=
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